1. Technical Field
The present invention relates to a voltage boosting power supply circuit and a boosted voltage control method, more particularly to a charge pump voltage boosting power supply circuit that employs a capacitor, as well as a boosted voltage control method.
2. Related Art
A charge pump power supply circuit is incorporated in each liquid crystal display panel driving IC (Integrated Circuit) employed for portable phones. This power supply circuit generates a panel driving voltage used for driving a liquid crystal display panel from a voltage (supply voltage) supplied from a battery or the like and supplies the generated voltage to the object driving IC. Many manufacturers are involved in portable phone markets and manufacturing various types of portable phones. Under such circumstances, such display panel driving ICs are required to have general-purpose properties and generate a predetermined driving voltage from any of various types of supply voltages without changing their settings.
Furthermore, such display panel driving ICs are also required to be reduced more in size to cope with liquid crystal display panels that are becoming narrower in frame width. And now that the picture quality is improved more and more due to an increase in the number of color tones, influences of the power supply circuit output voltage quality on picture quality cannot be ignored. This is why there has been a need of such a compact and high performance power supply circuit, that is, a compact power supply circuit that can prevent voltage falling to be caused by a load current. Consequently, chip sized and low voltage transistors favorable in performance have been used for those power supply circuits. The low voltage transistor has smaller on-resistance than the high voltage transistor when the same channel width is employed for both of the transistors. The use of such low voltage transistors, therefore, makes it possible to configure a low resistance switch smaller in size than a circuit that uses high voltage transistors.
Such a charge pump power supply circuit that generates a driving voltage from a supply voltage is disclosed in, for example, Japanese Patent Laid-Open Application No. 2005-20922. As shown in FIG. 1, this charge pump power supply circuit includes a voltage boosting circuit 790, a control circuit 780, a comparator 773, and a smoothing capacitor 799. The power supply circuit supplies an output voltage VDC 2 to a load circuit (not shown).
The voltage boosting circuit 790 includes transistors (switches) 791 to 794 and a voltage boosting capacitor 797. Each of the transistors 791 and 793 is a switch for applying a supply voltage VDC to the voltage boosting capacitor 797, thereby charging the capacitor 797. The transistor 792 is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor 797 that is already charged, thereby boosting the voltage of the capacitor 797. The transistor 794 is a switch for supplying a boosted voltage to the load circuit as a boosted output VDC 2.
The comparator 773 compares the charging voltage of the voltage boosting capacitor 797 with a reference voltage VR and outputs the comparison result to the control circuit 780. The control circuit 780 includes an AND circuit 781, a NAND circuit 782, and a NOT circuit 783. The control circuit 780 controls the on/off state of each of the transistors 791 to 794 of the voltage boosting circuit 790.
The output of the voltage boosting circuit 790 is smoothed by the smoothing capacitor 799 and the result is supplied to the load circuit. The smoothed output voltage VDC 2 is also supplied to the AND circuit 781, the NAND circuit 782, and the NOT circuit 783 of the control circuit 780, etc.
Next, there will be described the operation of this power supply circuit. A voltage Va of a node a is compared with the reference voltage VR in the comparator 773. The node a is connected to a terminal away far from the GND of the voltage boosting capacitor 797, the drain terminal of the transistor 793, and the source terminal of the transistor 794 respectively. The output of the comparator 773 becomes high when the voltage Va of the node a is lower than the reference voltage VR (Va<VR) and low when the voltage Va of the node a is higher than the reference voltage VR (Va≦VR).
When the level of the voltage boosting clock CLK is low, the gate level of each of the transistors 792 and 794 becomes high, so that those transistors are turned off. At this time, if the output level of the comparator 773 becomes high due to Va<VR, the level of the two inputs of the AND circuit 781 also becomes high. Consequently, the transistor 791 is turned on and the level of the two inputs of the NAND circuit 782 become high. Consequently, the transistor 793 is also turned on. At this time, the voltage Va of the node a is equal to the charging voltage VC of the voltage boosting capacitor 797. Thus the supply voltage VDC is applied to the voltage boosting capacitor 797, thereby the voltage boosting capacitor 797 is charged. In other words, while the level of the voltage boosting clock CLK is low and Va<VR is assumed, the voltage boosting capacitor 797 is kept charged in that period.
If the output level of the comparator 773 becomes low due to Va≧VR, that is, VC≦VR while the level of the voltage boosting clock CLK is low, the output of the AND 781 becomes low. As a result, the transistor 791 is turned off and the output level of the AND 782 becomes high, thereby the transistor 793 is also turned off. Consequently, the charging of the voltage boosting capacitor 797 stops. At this time, the voltage boosting capacitor 797 keeps the charging voltage as is without charging and discharging. The voltage boosting capacitor 797 is charged until the charging voltage VC becomes equal to the reference voltage VR.
When the level of the voltage boosting clock CLK is high, the level of the gates of the transistors 792 and 794 becomes low, so that those transistors 792 and 794 are turned on. At this time, the output level of the AND 781 becomes low, so that the transistor 791 is turned off and the output level of the NAND 782 becomes high, thereby the transistor 793 is turned off. Consequently, the connecting node between the voltage boosting capacitor 797 and the transistor 791 is applied the supply voltage VDC through the transistor 792 and the voltage Va of the node a is boosted to a value (VDC+VC) that is a sum of the supply voltage VDC and the charging voltage VC of the voltage boosting capacitor 797. This boosted voltage is supplied to the smoothing capacitor 799 through the transistor 794 that is turned on, thereby the voltage VDC2=(VDC+VC) is supplied to the load circuit as an initial value. Consequently, while the level of the voltage boosting clock CLK is high, it is assumed as a boosted voltage output period.
In the above power supply circuit, the charging voltage VC can be set with reference to the reference voltage VR in such a way and the voltage VC never exceeds the reference voltage VR. However, as shown in the case of the output voltage VDC2=(VDC+VC) just after a boosted voltage output period is set, the output voltage VDC2 is affected by a fluctuation of the supply voltage VDC. For example, when the supply voltage VDC is 3 volts, the reference voltage VR is set so as to obtain output voltage VDC2=5 volts. In an ideal case, the relationship between the supply voltage VDC and the output voltage VDC2 becomes as shown in FIG. 2. When the supply voltage VDC is 3 volts, the output voltage VDC2 is 5 volts. And if the reference voltage VDC falls, the output voltage VDC2 also falls, resulting in insufficient voltage. On the other hand, if the supply voltage VDC rises, the output voltage VDC2 also rises, thereby the element breakdown voltage might be exceeded. In other words, in the above power supply circuit, in order to keep the output voltage VDC2 constantly, the reference voltage VR should be varied in accordance with the supply voltage VDC.
FIG. 3 shows a circuit diagram of a charge pump power supply circuit disclosed in Japanese Patent Laid-Open Application No. 2005-278383. This power supply circuit includes a voltage boosting circuit 890, a comparison circuit 870, a control circuit 880, and a smoothing capacitor 899. The power supply circuit supplies an output voltage VDC2 to a load circuit (not shown).
The voltage boosting circuit 890 includes transistors (switches) 891 to 894 and a voltage boosting capacitor 897. The transistors 891 and 893 are switches for applying a supply voltage VDC to the voltage boosting capacitor 897, thereby charging the capacitor 897. The transistor 892 is a switch for connecting the supply voltage VDC serially to the voltage boosting capacitor 897 that is already charged, thereby boosting the voltage of the capacitor 897. The transistor 894 is a switch for supplying the boosted voltage to the load circuit as a boosted voltage output VDC2.
The comparison circuit 870 includes a comparator 873 and resistance elements 871 and 872. Each of the resistance elements 871 and 872 divides the output voltage VDC2 of the voltage boosting circuit 890 to generate a comparison voltage VCMP. The comparator 873 compares the comparison voltage VCMP with the reference voltage VR and outputs the comparison result VCTL to the control circuit 880. The control circuit 880 includes a level shift circuit 883, a NAND circuit 881, and a NOT circuit 882. The control circuit 880 controls the on/off state of each of the transistors 891 to 894 of the voltage boosting circuit 890 according to the comparison result VCTL output from the comparison circuit 870 and the voltage boosting clock CLK.
The output of the voltage boosting circuit 890 is smoothed by the smoothing capacitor 899 and the result is supplied to the load circuit. The smoothed output voltage VDC2 is also supplied to the NAND circuit 881, the NOT circuit 882, the level shift circuit 883 of the control circuit 880, etc.
Next, there will be described the operation of this power supply circuit with reference to FIGS. 4A to 4D. When the level of the voltage boosting clock CLK is low (FIG. 4A), the output level of the NAND circuit 881 becomes high and the transistors 891 and 893 are turned on while the transistors 892 and 894 are turned off. Consequently, the supply voltage VDC is applied to the voltage boosting capacitor 897, which is thus charged until the charging voltage VC becomes equal to the supply voltage VDC (FIG. 4B).
While the level of the voltage boosting clock CLK is high (FIG. 4A), if the level of the comparison result VCTL is high, the output of the NOT circuit 882 becomes high (FIG. 4D). And because the output voltage VDC2 is discharged until it goes lower than the predetermined voltage V2 (FIG. 4D), the output level of the comparison circuit 870 is high and the output level of the NAND circuit 881 is low. Consequently, the transistors 891 and 893 are turned off while the transistors 892 and 894 are turned on. In other words, the supply voltage VDC is applied to the connecting node between the voltage boosting capacitor 897 and the transistor 891 through the transistor 892, thereby the voltage VC− of the connecting node is assumed as a voltage VDC as shown in FIG. 4C. Consequently, the voltage of the connecting node between the voltage boosting capacitor 897 and the transistor 893 is boosted by the same voltage as the supply voltage VDC. If the voltage of the voltage boosting capacitor 897 is assumed as VC, the voltage VC+ of the connecting node between the voltage boosting capacitor 897 and the transistor 893 becomes VDC+VC (FIG. 4B). The connecting node between the voltage boosting capacitor 897 and the transistor 893 is connected to the smoothing capacitor 899 through the transistor 894 and the voltage VDC2=(VDC+VC) is supplied to the connecting node. And because the charging voltage VC is kept charged until it becomes equal to the supply voltage VDC, the output voltage VDC2 becomes double the voltage VDC instantaneously (FIG. 4D).
The comparator 873 compares the comparison voltage VCMP with the reference voltage VR. The VCMP is obtained by dividing the output voltage VDC2 through any of the resistance elements 871 and 872. The output level of the comparator 873 becomes high when the comparison voltage VCMP is lower than the reference voltage VR (VCMP<VR) and becomes low when the comparison voltage VCMP is higher than the reference voltage VR (VCMP≦VR). When the output level of the comparison circuit 870 is high, the output level of the NAND circuit 881 of the control circuit 880 becomes low, thereby the voltage boosting circuit 890 keeps discharging. If the output level of the comparison circuit 870 becomes low, the output level of the NAND circuit 881 becomes high, thereby the voltage boosting circuit 890 stops discharging.
When the state of the voltage boosting circuit 890 is switched from charging to discharging, the output voltage VDC2 becomes double the VDC. Thus the output level of the comparison circuit 870 becomes low and the state of the voltage boosting circuit 890 is switched from discharging to charging. Consequently, the smoothing capacitor 899 is discharged and the output voltage VDC2 falls gradually in accordance with the power consumption of the load circuit. If the comparison voltage VCMP obtained by dividing the output voltage VDC2 becomes lower than the reference voltage VR, the output level of the comparison circuit 870 becomes high and the state of the voltage boosting circuit 890 is switched to discharging.
In this power supply circuit, the output voltage VDC2 is controlled so that the comparison voltage VCMP obtained by dividing the VDC2 is equalized to the reference voltage VR as described above. Consequently, this power supply circuit can keep the output voltage VDC2 at a predetermined voltage V2 without changing its setting regardless of the changes of the supply voltage VDC. However, the voltage boosting capacitor 897 is charged up to the supply voltage VDC during the charging period, so that the output voltage VDC2, as shown in FIG. 4D), goes over the predetermined voltage V2 just after discharging and becomes about double the supply voltage VDC. In other words, an element to which the output voltage VDC2 is supplied should be set at a high breakdown voltage so as to withstand the instantaneous output voltage VDC2. Rising of this instantaneous output voltage VDC2 causes random noise generation. The output voltage VDC2, as shown in FIG. 5, is assumed as a power supply of a source driver and such noise affects the output of the source driver. And the fluctuation of the source driver causes horizontal stripes to appear on the screen, resulting in degradation of the display quality if the source driver output is not synchronized with the panel display frequency.
As described above, in a conventional power supply circuit, obtaining a predetermined output voltage from any of wide ranged supply voltages has been confronted with various problems. For example, it has been required to change settings in accordance with the supply voltage, noise is generated, and the element breakdown voltage is exceeded.
Under such circumstances, it is an exemplary feature of the present invention to provide a power supply circuit capable of obtaining a predetermined output voltage from any of wide ranged supply voltages without changing the settings.